1. Field of the Invention
The present invention relates to cache control, and in particular, to cache control connected to computer applications.
2. Description of the Related Art
For instruction codes that are stored in a main memory, part of the frequently executed instruction code is stored in a cache memory, which reduces an access count to a slow-operating main memory and improves high-speed processing.
However, known caches have not been controlled in accordance with the operations of applications. To increase processor frequency and to meet a demand for high performance, a need for making effective use of the computer processor's cache memory has been recently increasing. In particular, when a commercial application (e.g. web application) server processes a client request, it often creates memory objects that are used only in a specific request process and that become unused after completion of the process. With such a memory access pattern, the use of a normal LRU algorithm (evicting the least recently used data items into a memory) causes unnecessary data to be left in a cache after completion of a transaction process, which hinders effective use of the cache memory.
A known cache memory system in the related art allows software to control the operation aggressively (see PCT International Publication No. WO 2006/112111). According to this system, an attribute control means causes a cache memory to execute a predetermined operation as a processor executes a predetermined instruction. However, this system does not perform cache control based on the operation of an application, which hinders efficient cache control in an application server that repeats creation and deletion of memory objects.
A method in the related art is a method for estimating a memory reuse distance per cache line with a compiler (see Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, Charles C. Weems, “Using the Compiler to Improve Cache Replacement Decisions,” Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques, p. 199, Sep. 22-25, 2002). At the first access (last use) of an access having a long reuse distance, the CPU writes information of the reuse distance in the tag bit of a cache line. Therefore, the compiler generates a special load/store instruction to write a tag value in advance as an instruction to execute a memory access. When there is a need for evicting a line from the cache, the cache selects a line having a long reuse distance as a victim candidate, with priority, using the tag value. This allows lines that should be evicted before reuse to be evicted aggressively and lines other than those to be held as much as possible. This method depends on the estimation of a reuse distance by the compiler. However, existing commercial servers generally process a plurality of tasks in parallel, and the reuse distance greatly changes with combinations of tasks processed at the same time during execution, which makes the estimation by the compiler extremely difficult.
Another related art is a prefetch instruction installed in Intel processors or the like (see published patent application US 2006/0101208 A1). When prefetch is performed using this instruction, a flag is put on a corresponding line in a cache. With this flag on, the line is not stored in a lower layer cache when evicted, which can therefore avoid contamination of the lower layer cache. However, according to this method, if the total amount of short-life data exceeds the cache size, a cache miss to access a main memory frequently occurs.
Thus, since the methods of the foregoing related art do not involve cache control based on the operation of applications, an improvement in performance of commercial servers, such as web application servers, is needed.